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1 copyright ? cirrus logic, inc. 1999 (all rights reserved) cirrus logic, inc. p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com AN83 application note &u\vwdo/$1? cs8900a ethernet controller technical reference manual by deva bodas revised by james ayres apr 99 AN83rev2
AN83 2 AN83rev2 table of contents schematic checklist ............................................................................................................ .......................4 software checklist ............................................................................................................. .......................5 introduction to cs8900a technical reference manual ..............................................................6 hardware design ................................................................................................................ ..........................7 cs8900a: connecting to non-isa bus systems ...................................................................................7 the cs8900a architecture....................................................................................................... ......................7 isa bus ........................................................................................................................ ............................8 cs8900a in i/o mode ............................................................................................................ ..................8 cs8900a in memory mode......................................................................................................... .............8 dma interface of the cs8900a................................................................................................... .............8 selection of i/o, memory and dma modes ......................................................................................... ...........9 design example: cs8900a interface to mc68302 ................................................................................... .....9 address generation ............................................................................................................. ....................9 read and write signals ......................................................................................................... ................10 sbhe signal .................................................................................................................... ......................10 other control signals.......................................................................................................... ...................10 status signals from cs8900a .................................................................................................... ...........11 databus (sd[0:15]) connection.................................................................................................. ..................11 checklist for signal connections to the cs8900a ................................................................................ .......11 eeprom optional................................................................................................................ ........................11 design example: cs8900a interface to cirrus logic cl-ps7111 ...............................................................12 design example: cs8900a interface to hitachi sh3 ............................................................................... ....12 summary ........................................................................................................................ ..............................12 ethernet hardware design for embedded systems and motherboards ..........................15 general description ............................................................................................................ ...................15 board design considerations .................................................................................................... ............15 crystal oscillator ............................................................................................................. ................15 isa bus interface .............................................................................................................. ..............15 external decode logic .......................................................................................................... ..........15 eeprom ......................................................................................................................... ................15 leds........................................................................................................................... .....................18 10base-t interface ............................................................................................................. ...........18 10base-2 and aui interfaces .................................................................................................... .....18 logic schematics............................................................................................................... ....................18 component placement and signal routing ...................................................................................... ..20 bill of material ............................................................................................................... .........................20 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ crystal lan, streamtransfer, packetpage, and smart analog are trademarks of cirrus logic. ethernet is a registered trademark of xerox corp.. artisoft and lantastic are registered trademarks of artisoft, inc.. banyan a nd vines are registered trademarks of banyan systems.. digital and pathworks are registered trademarks of digital equipment corporation.. intel is a registered tr ademark of intel corporation.. lan server and ibm are registered trademarks of international business machines corp.. microsoft, lan manager, windows 95, wind ows for workgroups, and windows nt are registered trademarks of microsoft.. novell and netware are registered trademarks of novell, inc.. sco is a registered trademark of santa cruz organization, inc .. unix is a registered trademark of at&t technologies, inc. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
AN83 AN83rev2 3 low cost ethernet combo card reference design: crd8900 .................................................. 21 general description ............................................................................................................ ................... 21 board design ................................................................................................................... ...................... 21 crystal oscillator ............................................................................................................. ................ 21 isa bus interface .............................................................................................................. .............. 21 external decode logic .......................................................................................................... .......... 21 eeprom......................................................................................................................... ................ 21 socket for optional boot prom .................................................................................................. ... 21 leds ........................................................................................................................... .................... 26 10base-t interface ............................................................................................................. ........... 26 aui interface .................................................................................................................. ................. 26 10base-2 interface ............................................................................................................. ........... 27 logic schematics............................................................................................................... .................... 27 component placement and routing of signals ..................................................................................... 27 bill of material ............................................................................................................... ......................... 27 addressing the cs8900a: i/o mode, memory mode .................................................................................. .27 i/o mode ....................................................................................................................... ......................... 27 memory mode.................................................................................................................... .................... 31 lower memory mode .............................................................................................................. ........ 31 extended memory mode ........................................................................................................... ...... 31 layout considerations for the cs8900a .......................................................................................... ............ 35 general guidelines ............................................................................................................. ................... 35 power supply connections....................................................................................................... ............. 35 two layered printed circuit board (pcb) ...................................................................................... 35 multi-layered printed circuit board ............................................................................................ ..... 35 routing of the digital signals................................................................................................. ................ 35 routing of the analog signals .................................................................................................. ............. 35 recommended magnetics for the cs8900a ....................................................................................... 44 jumperless design.............................................................................................................. ....................... 45 serial eeprom.................................................................................................................. .......................... 45 reset configuration block ...................................................................................................... ............... 45 driver configuration information............................................................................................... ............. 47 format of driver configuration block........................................................................................... .......... 47 ieee physical address .......................................................................................................... ......... 49 isa configuration flags ........................................................................................................ .......... 49 packetpage memory base......................................................................................................... ..... 50 boot prom memory base......................................................................................................... .... 50 boot prom mask ................................................................................................................ .......... 50 transmission control ........................................................................................................... ........... 50 adapter configuration word..................................................................................................... ....... 51 eeprom revision................................................................................................................ .......... 51 manufacturing date............................................................................................................. ............ 52 ieee physical address (copy)................................................................................................... ..... 52 16-bit checksum ................................................................................................................ ............. 52 eisa id ........................................................................................................................ ................... 52 serial number .................................................................................................................. ............... 53 serial id checksum ............................................................................................................. ........... 53 maintaining eeprom information................................................................................................. ........ 54 embedded designs ............................................................................................................... ....................... 54 bios-based design considerations............................................................................................... ....... 54 driver interface with bios-based configuration ................................................................................. .. 54 obtaining ieee addresses ....................................................................................................... ................ 55 device drivers and setup/installation software....................................................................... 56 dos setup and installation utility ............................................................................................. ................... 56 installation procedure ......................................................................................................... ................... 56 contacting customer support at cirrus ....................................................................................... 57 cirrus web site ................................................................................................................ ............................ 57
AN83 4 AN83rev2 schematic checklist before getting into the meat of the technical refer- ence manual here is a schematic checklist. its pre- sented here, at the beginning, to help the hardware designer implement the design quickly and easily. - no caps across the crystal. the cs8900a implements these internally. - 4.99k 1% resistor between pin 93 and pin 94. a common mistake is the resistor is connected to vcc instead of ground. - reset is active high, not active low. - check addressing. - on non-isa systems, if the processor is big endian, it may be beneficial to byte swap the data lines to minimize byte swapping in software. - sbhe (16 bit mode) -- must be low on io or mem address. and it must toggle at least once to put the cs8900 in 16 bit mode. - io and memory accesses: sbhe, aen, etc. must be stable for 10ns (read) and 20ns (write) before access. - iochrdy - generally not connected in non-isa bus. - chipsel (active low). tie to ground if not using elcs. - make sure interrupt line is active high. it is best to put a pull down (10k) on int line since selected irq line is tristated during software initiated reset. - elcs should be pulled to ground if not used. - eedatain should be pulled to ground if not used. - 10base-t circuit -- no caps on tx lines between isolation transformer and 10 base-t connector. - 10base-t circuit -- no center tap caps on isolation transformer and 10 base-t connector. good to have pads, don't populate except for emi problems. - isolation transformer -- start with one that does not have a common mode choke. if there are emi considerations, then use one with common mode choke. the pin outs are the same. for 3.3v operation, use a transformer with 1:2.5 turns ration on tx and 1:1 on rx like the halo tg41-2006n. - for emi problems, 1) add choke, 2) add center tap caps on isolation transformer - if using a shielded rj45 connector, make sure the shield pins are connected to chassis ground. - aen connected to ground if not using dma. - aen can be used as an active low chip select if not using dma. - aui interface -- use a 1amp fuse. mau can use .5amps even better use a thermistor ("poly switch"). also, use a diode so can't back-drive from an externally powered mau. use a halo tnt integrated module to simplify 10base2 interface. - tx series termination resistors are r: 24.3 ohm 1% (8 ohm 1% for 3.3v) - rx shunt termination resistor is 100 ohm - put a 68pf shunt across tx on primary side (560pf for 3.3v) - don't use split analog/digital power and ground planes. - void ground/power plane from transformer to rj45 - put .1uf cap on each supply pin very close to cs8900 the schematic checklist and the example connec- tion diagrams to the hitachi sh3, cirrus logic cl- ps7111 and the motorola mc68302 microproces- sors should make clear the necessary the hardware connections for a wide variety of situations.
AN83 AN83rev2 5 software checklist - when servicing the interrupt always read the interrupt status queue (isq) first. process that individual event before reading the isq again. - having read an isq event indicating a valid recieve frame, never read the isq again before either 1) reading in the entire current receive frame or 2) issuing an explicit skip command. either of these actions will correctly clear that frame from the cs8900as internal memory. - always continue reading and processing isq events until reading a 0x0000 from the isq. - after a software or hardware reset, always wait until the selfstatus register, bit 7 (initd) is set before reading or writing any other registers. - allow only one transmit in progress at any given time. since the chip dynamically allocates memory between transmit and recieve frames, it is possible to fill the internal buffers with transmit frames. this would prevent reception. - dont reinvent the wheel. port one of the sample drivers, if there isnt a driver for your operating system. you can find sample drivers at http://www.cirrus.com/drivers/ethernet/.
AN83 6 AN83rev2 introduction to cs8900a technical reference manual this technical reference manual provides the in- formation which will be helpful in designing a board using the cs8900a, programming the asso- ciated eeprom, and installing and running the cs8900a device drivers. it is expected that the user of this technical reference manual will have a general knowledge of hardware design, ethernet, the isa bus, and networking software. recom- mended sources of background information are: isa system architecture by shanley and anderson, mindshare press, 1992, isbn 1- 881609-05-7 ethernet, building a communication infra- structure , by hegering and lapple, addison- wesley, 1993, isbn 0-201-62405-2 netware training guide: networking technol- ogies , by debra niedenmiller-chaffis, new riders publishing, isbn 1-56205-363-9 as shown in the figure 1, the cs8900a requires a minimum number of external components. the eeprom stores configuration information such as interrupt number, dma channel, i-o base address, memory base address, and ieee individual ad- dress. the eeprom can be eliminated on a pc motherboard if that information in stored in the sys- tem cmos. note also that the boot prom is only needed for diskless workstations that boot dos at system power up, over the network. also, the leds are optional. the hardware design considerations for both moth- erboards and adapter cards are discussed in hardware design on page 7. the ee- prom programming considerations are described in jumperless design on page 45. cirrus provides a complete set of device drivers, as discussed in device drivers and set- up/installation software on page 56. the drivers reside between the networking operat- ing system (nos) and the cs8900a. on the cs8900a side, the drivers understand how to pro- boundary ram isa bus logic memory manager media access control (mac). ethernet protocol processing. eeprom control encoder, decoder & pll 10base-t rx filters & receiver 10base-t tx filters & transmitter aui transmitter aui collision aui receiver clock power manage scan test logic led control eeprom : stores configuration information & ieee address 57 pins isa bus boot prom : used to boot diskless workstations. aui transformer (attachment unit interface) 10base-t transformer figure 1. hardware application summary
AN83 AN83rev2 7 gram and read the cs8900a control and status reg- isters, and how to transfer user data between the cs8900a and the pc main memory via the isa bus. on the nos side, the drivers provide the stan- dardized services and functions required by the nos, and hide all details of the cs8900a hardware from the nos. the eeprom device programs the cs8900a whenever the a hardware reset occurs, and call also store state/configuration information for the driver. cirruss software driver ( &u\vwdo /$1? ) distribu- tion policy is as follows. the cs8900a developer kit contains a single-user copy of object code which is available only for internal testing and evaluation purposes. this object code may not be distributed without first signing a license for distribu- tion of executable software, which may be obtained by contacting your sales represen- tative. the license for distribution of executable software gives you unlimit- ed, royalty-free rights to distribute cirrus-provided object code. hardware design this section give design guidance for both embed- ded and adapter card designs, including recommen- dations for dealing with the upper isa address lines (la[20:23]), choosing transformers, and laying out the board. cs8900a: connecting to non-isa bus systems the cs8900a includes a direct interface to the isa bus. at the same time, the cs8900a offers a com- pact, efficient, and cost-effective, full-duplex ethernet solution for non-isa architectures. the purpose of this section is to illustrate how to inter- face the cs8900a to non-intel and non isa sys- tems. design examples include the mc68302, cirrus logic cl-ps7111 arm and hitachi sh3. the cs8900a architecture the cs8900a is a highly integrated ethernet con- troller chip. it includes the digital logic, ram and analog circuitry required for an ethernet interface. this high level of integration allows a product de- signer to design an ethernet interface in 1.5 square inches of space on a printed circuit board. the cs8900a has a powerful memory manager that dy- namically allocates the on-chip memory between transmit and receive functions. the on-chip mem- ory manager performs functions in hardware that are many times done by software. this reduces loading on the cpu and on the bus connected to the cs8900a. in fact, for 10 megabit ethernet, the cs8900a is the highest throughput solution in the market. the integration of the analog transmit waveform filtering makes it easier to design a board that will pass emc testing. when the analog filters are ex- ternal, the pcb traces have fast edge digital wave- forms coming out of the ics 10base-t transmitter. the presence of high frequency energy in the fast edges causes major problem during emc tests, such as fcc part 15 class (b) or cispr class (b). the 10base-t signals driven out of the cs8900a are internally filtered with a 5 th order butterworth filter and the signals lack fast edges. lack of high frequency signals makes it straight forward to design a card that meets fcc class (b) or even cispr class (b) requirements. applications operating system software e.g., file manager network operating system e.g., novell or microsoft cs8900 - specific device drivers: e.g., ndis & odi compatible drivers cs8900 registers & memory eeprom figure 2. software application summary
AN83 8 AN83rev2 isa bus an isa bus is a simple, asynchronous bus that can easily be made to interface to most synchronous or asynchronous buses. an isa bus has separate ad- dress and data lines as well as separate control lines for read and write. isa supports io address space of 64k bytes and memory address space 32 mega bytes. cs8900a in i/o mode when the cs8900a is used in an io mode, it re- sponds in the io address space of the isa. the cs8900a responds to an io access when - either of the bus io command lines (ior or iow ) is active, - the address on bus signals sa[0:15] matches the address in the cs8900a io base address register, and - bus signals aen, refresh , test , sleep and reset are inactive. all other control signals are ignored for the io op- eration. in an io mode, the cs8900a uses 16 bytes of io address space. the address map for this mode is described in table 4.5 in the cs8900a datasheet. cs8900a in memory mode when the cs8900a is used in memory mode, the cs8900a responds in the memory address space of the isa bus. the cs8900a responds to a memory mode access when - the chipsel pin is active, - either of the bus memory command lines (memr or memw ) is active, - both of the io command lines (ior and iow ) are inactive, - the address on bus signals sa[0:19] matches the address in the cs8900as memory base address register, - memorye (bit a) in the cs8900as busctl (register 17) is active and, - bus signals aen, refresh , test , sleep and reset are inactive. in memory mode, all the internal registers of the cs8900a can be accessed directly via memory reads/writes. please refer to the cs8900a datasheet for the memory address map. dma interface of the cs8900a the cs8900a can interface to an external 16-bit dma channel for receive operations. a dma- mode receive operation can be selected by setting either rxdmaonly (bit 9) or autorxdma (bit 10) in the cs8900as rxcfg (register 3) register. the cs8900a will request services of an external dma after a receive frame is accepted by the cs8900a, completely received and stored in on chip ram of the cs8900a. the cs8900a gener- ates a request for dma access (drqx) signal when it has at least one receive frame that can be trans- ferred to the system memory. the external dma channel should assert dmack signal when it is ready to transfer data. the dma controller gener- ates address for the system memory and asserts the aen signal. when dmack and aen signals are asserted, the cs8900a provides 16 bits of frame data for every pulse of the ior signal. notice that the cs8900a ignores address on the sa address lines for this operation. in this way the cs8900a supports direct mode of operation of dma. in direct mode, the external dma controller gener- ates addresses for the system ram, and generates the appropriate control signals for the ram and io device. the data moves directly from the io device to the ram. in the case of the cs8900a, the dma controller generates a write signal for ram and a read signal for the cs8900a. the data flows di- rectly from the cs8900a to the system ram. the direct mode of dma operation is 100% more effi- cient than typical read-followed-by-write dma operation. the length of time that the cs8900a holds the drq signal active depends upon the dmaburst (bit b) bit of the busctl (register 17) register. if the dmaburst is clear, the drq remains active as
AN83 AN83rev2 9 long as the cs8900a contains frames completely received. if n words are to be transferred from the cs8900a to the system ram, the drq signal re- mains active until the (n-1) th word is transferred. if the dmaburst is set, then the cs8900a deasserts drq signal for 1.3 s after every 28 s. this op- tion is provided so that in a system where multiple dma channels are operational, the dma used for the cs8900a will not take over the system bus for long periods of time. selection of i/o, memory and dma modes the cs8900a always responds to all io-mode re- quests. after any reset, the cs8900a responds to default io base address of 0300h. however, this default io address can be changed by writing a dif- ferent base address into a eeprom connected to the cs8900a. after any reset, the cs8900a reads the contents of the eeprom. if the eeprom is found valid, then the information in the eeprom is used by the cs8900a to program its internal reg- isters. memory mode in the cs8900a can be enabled by programming a proper base-address value in the memory base address register and setting the memorye bit. enabling of the memory mode can be done by software or through an eeprom con- nected to the cs8900a. in an io mode, the cs8900a takes the minimum space (16 bytes) in the system address space. for systems where the address space limited, the io mode is a proper choice. the memory mode is the most direct and efficient mode of operation for the cs8900a. in the mem- ory mode the cs8900a occupies 4k of the address space. the software can access any of the internal registers of the cs8900a directly. this reduces ac- cesses to the cs8900a by half when accessing reg- isters. in a system design, even if cs8900a is used in the memory mode, the designer should make provi- sions for accessing the cs8900a in the io mode. this dual-mode access has two advantages. 1) if an eeprom is not used in the ethernet de- sign, the application can address the cs8900a in io mode (0300h) in order to enable memory mode. 2) when the eeprom is used, the eeprom is usually blank when a board is manufactured. the cs8900a must be accessed in io mode in order to program the eeprom. use of dma for receive is efficient in a multi-task- ing environment where the cpu could be busy ser- vicing several higher priority tasks before it can service receive frames off the ethernet wire. design example: cs8900a interface to mc68302 in this example the cs8900a is connected to mo- torola micro-controller mc68302. please refer to figure 3 to check the connection of control signals between cs8900a and motorolas micro-control- ler mc68302. address generation the mc68302 has address decode generation logic internal to the micro-controller. it generates chip select signals such as cs1 . in this example the cs1 is used to access the cs8900a in io as well as in memory mode. the behavior of the cs1 signal from the mc68302 is governed by values pro- grammed in the cs1 base address register and the cs1 option register. for example, if the cs1 base address register is programmed as 3a01h, the cs1 will have a base address of d00xxxh. the cs1 op- eration register controls the address range, number of wait states (to be inserted automatically), etc. it is recommended that the cs8900a be assigned 8k of address space (0d00000h-0d01fffh). memo- ry mode of the cs8900a is enabled with the mem- ory base address register with a value 001000h. the address line a12 separates io address space and memory address space. when a12 is low, the
AN83 10 AN83rev2 cs8900a is accessed in an io mode and when a12 is high, the cs8900a is accessed in memory mode. when the mc68302 generates address 0d00300h, the address seen by the cs8900a will be 00300h with one of the io commands (ior or iow ) active. similarly when the mc68302 generates address 0d01400h, the address seen by the cs8900a will be 01400h with one of its memory commands (memr or memw ) active. for a mc68302, you can also specify the number of wait states that should be inserted automatically when address space assigned to cs1 is accessed. the number of wait states used depends upon the clock input to the mc68302. please do a complete timing analysis before defining wait states. read and write signals the combination of or gates and an inverter shown in figure 3, generates io commands (ior , iow ) as well as memory commands (memr , memw ) for the cs8900a. since the cs1 gates these signals, the io or memory commands are not generated unless the address on the address bus is stable. further, for an access in memory mode, an io command is not active. sbhe signal the cs8900a is a 16 bit device and it should be used as a 16 bit device. however, after a hardware or software reset, the cs8900a behaves as an 8 bit device. any transition on pin sbhe places the cs8900a into 16-bit mode. further, for a 16-bit access, the sbhe pin of the cs8900a must be low. in the design example, the cpu address line a0 is connected to sbhe . before any access to the cs8900a, the design must guarantee one transition on sbhe pin. other control signals all other control signals can be tied high or low. the signal refresh , test , sleep , aen should be tied inactive. 74f32 74f32 74f32 74f32 74f04 74f04 cs1* r/w* sbhe* sa0 sa [1:11] sa12 sa[13:19] memw* iow* memr* ior* intrq0 uds*/a0 a[1:11] a12 cs1* r/w* int* cs8900 mc68302 interrupt controller figure 3. connection of cs8900a to mc68302
AN83 AN83rev2 11 status signals from cs8900a there are several status signals that are output from the cs8900a, such as iochrdy, iocs16 , mcs16 , etc. in the most embedded designs, they are not needed. those pins from the cs8900a should be left open. databus (sd[0:15]) connection all the internal registers of the cs8900a are 16 bit wide. for all the registers, bit f of the register is ac- cess via sd15 and bit 0 of register is accessed via sd0. to be compatible with byte ordering with isa bus, the cs8900a provides the bytes received from the ethernet wire in the following fashion. assume that the data received from the ethernet wire is 01, 02, 03, 04, 05, ... where the 01 is the first byte, 02 is the second byte and so on. when the cs8900a transfers that data to the host cpu, the data words are read from the cs8900a as 0201, 0403, etc. for certain microprocessor systems, the designer may prefer to read the data as 0102, 0304, etc. in such a case, the databus connections to the cs8900a can be altered by connecting the cpu databus d[0:7] to the sd[8:15] pins of the cs8900a and the cpu databus d[8:15] to the sd[0:7] pins of the cs8900a. in such a case, make sure that all the register and bit definitions in the cs8900a are also byte swapped. information that is normally appears at bits [0:7] will now appear on bits [8:15], and in- formation that usually appears on bits [8:15] will now appear on bits [0:7]. checklist for signal connections to the cs8900a please refer to the datasheet for the cs8900a for the pin assignment and pin descriptions of various signals discussed in this section. clock: there are two options for the clock connec- tion to the cs8900a. you may connect a 20.000 mhz crystal between xtl1 (pin 97) and xtl2 (pin 98) pins of the cs8900a. or, if there a 20 mhz clock available in the system, it can be con- nected to the xtl1 (pin 97) pin of the cs8900a. it is important that this clock be ttl or cmos with 40/60 duty cycle and 50 ppm accuracy. sbhe signal: it is recommended that the cs8900a be used in 16-bit mode. after a hard- ware or software reset, the cs8900a comes up as an 8-bit device. a transition on sbhe signal (pin 36) makes the cs8900a function as a 16-bit de- vice. after this transition, the sbhe can be kept low. for a 16-bit access of the cs8900a, the sbhe and address line sa0 (pin 37) must be low. un-aligned word accesses to the cs8900a are not supported. in a system, the sbhe line can be con- nected to address line sa0. in such a case, after a hardware or software reset, do a dummy read from an odd address to provide transition on the sbhe line. for memory mode, there is one more alterna- tive for the sbhe connection. for a memory mode operation, if a chipsel pin is controlled by an ex- ternal chip select, the chipsel can be connected to the sbhe . in this case, after a hardware and software reset, do a dummy access to the cs8900a and ignore data. eeprom optional the cs8900a has an interface for a serial ee- prom. most of the networking applications use this eeprom to store ieee mac (media access control) address. since the cs8900a supports 1 or 2 kbits of eeprom, the eeprom is also used to store information such as hardware configuration, software driver configuration, etc. any location in the eeprom can be read or written through the cs8900a. you will require eeprom if the io address for the cs8900a has to be other then 0300h, or the only mode supported by the cs8900a is memory mode. for all other cases an eeprom is optional. how- ever, most of the software drivers supplied by cir- rus assume that there is an eeprom connected to the cs8900a or driver configuration data is stored
AN83 12 AN83rev2 in bios. if the designer intends to use cirrus sup- plied drivers and does not use an eeprom or store driver configuration data in bios, then cirrus sup- plied drivers must be modified by the designer. we recommend that the system store the individual ieee mac address in a non-volatile memory somewhere in the system, and that the end-user of the system not be allowed to create an arbitrary ad- dress. in a lan, the existence of network nodes that use the same mac address will cause severe network problems including destruction of data and failure of various network nodes. design example: cs8900a interface to cirrus logic cl-ps7111 this design is similar to the mc68302 except that only the i/o mode data access is supported. this completely elimiates glue logic. see figure 4. the highlights of the design are: - cs8900a i/o space mapped into 7111 memory - 3 address lines - offset by 1 due to 7111s 32 bit data accesses - a8 and a9 tied high - aen used as active low chip select - sbhe tied to 7111 chip select - only 16 bit accesses design example: cs8900a interface to hitachi sh3 this design is almost identical to the cl-ps7111 connection diagram. it uses i/o mode only, elimi- nating glue logic. see figure 5. the highlights of the design are: - cs8900a i/o space mapped into sh3 memory - 3 address lines - a0 is tied to ground. - a8 and a9 tied high - aen used as active low chip select - sbhe tied to sh3 chip select - inverter on the irq line. - only 16 bit accesses summary the cs8900a can be interfaced to most non-isa system with very minimum or no external logic. this allows a low cost, small size and very efficient ethernet solution for non-isa systems. cirrus logic will provide support for non-isa designs, including logic schematic review and layout review for design engineers. those reviews help prevent logic errors, and help to minimize emi emissions.
AN83 AN83rev2 13 7111 d0-d15 7111 mnwe# 7111 mnoe# reset 7111 a4 7111 a3 7111 a2 7111 intrq3 7111 cs2# rxd- rxd+ txd- txd+ 3.3v 3.3v 3.3v 3.3v u114 cs8900a-cq3 37 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54 58 59 60 65 66 67 68 71 72 73 74 27 26 25 24 21 20 19 18 28 29 62 61 49 63 75 34 33 64 32 31 30 35 15 13 11 16 14 12 3 6 5 4 9 22 56 69 90 85 95 8 10 23 55 57 70 1 89 86 94 96 77 76 93 84 83 80 79 82 81 92 91 88 87 78 99 100 17 97 98 2 7 36 sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 sa16 sa17 sa18 sa19 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 memw memr iow ior refresh aen r eset memcs16 iocs16 iochrdy intrq0 intrq1 intrq2 intrq3 dmarq0 dmarq1 dmarq2 d mack0 d mack1 d mack2 eecs eedatain eedataout eesk dvdd1 dvdd2 dvdd3 dvdd4 avdd1 avdd2 avdd3 dvss1 dvss1a dvss2 dvss3 dvss3a dvss4 avss0 avss1 avss2 avss3 avss4 h wsleep t estsel res do- do+ di- di+ ci- ci+ rxd- rxd+ txd- txd+ bstatus/hc1 linkled/hc0 lanled csout xtal1 xtal2 elcs c hipsel sbhe 560pf 20mhz led led 4.99k 8 8 100 510 510 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf figure 4. cs8900a interface to cirrus logic cl-ps7111
AN83 14 AN83rev2 sh3 a2 sh3 irq0 reset sh3 ro# chip select# sh3 we1# sh3 [d15:d0] sh3 a1 sh3 a3 rdx- rxd+ txd- txd+ 3.3v 3.3v 3.3v 3.3v 510 0.1uf 510 cs8900a-cq3 37 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54 58 59 60 65 66 67 68 71 72 73 74 27 26 25 24 21 20 19 18 28 29 62 61 49 63 75 34 33 64 32 31 30 35 15 13 11 16 14 12 3 6 5 4 9 22 56 69 90 85 95 8 10 23 55 57 70 1 89 86 94 96 77 76 93 84 83 80 79 82 81 92 91 88 87 78 99 100 17 97 98 2 7 36 sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 sa16 sa17 sa18 sa19 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 memw memr iow ior refresh aen reset memcs16 iocs16 iochrdy intrq0 intrq1 intrq2 intrq3 dmarq0 dmarq1 dmarq2 dmack0 dmack1 dmack2 eecs eedatain eedataout eesk dvdd1 dvdd2 dvdd3 dvdd4 avdd1 avdd2 avdd3 dvss1 dvss1a dvss2 dvss3 dvss3a dvss4 avss0 avss1 avss2 avss3 avss4 hwsleep testsel res do- do+ di- di+ ci- ci+ rxd- rxd+ txd- txd+ bstatus/hc1 linkled/hc0 lanled csout xtal1 xtal2 elcs chipsel sbhe led 4.99k 0.1uf led 0.1uf 20mhz 0.1uf 0.1uf 0.1uf 0.1uf 560pf 8 8 100 figure 5. cs8900a interface to hitachi sh3
AN83 AN83rev2 15 ethernet hardware design for embedded systems and motherboards this section describes the hardware design of a four-layer, 10base-t solution intended for use on pc motherboards, or in other embedded applica- tions. the goal of this design is minimal board space and minimal material cost. therefore, a num- ber of features (bootprom, aui, 10base-2) are not supported in this particular pcb design. an ex- ample of this circuit is included in this technical reference manual, and is implemented in an isa form factor. this same circuit can be implemented directly on the processor pcb. general description the small footprint, high performance and low cost of the cs8900a ethernet solution, makes the cs8900a an ideal choice for embedded systems like personal computer (pc) mother boards. the very high level of integration in the cs8900a re- sults in a very low component count ethernet de- sign. this makes it possible to have a complete solution fit in an area of 1.5 square inches. board design considerations crystal oscillator the cs8900a, in this reference design, uses a 20.000 mhz crystal oscillator. the cs8900a has internal loading capacitance of 18pf on the xtal1 and xtal2 pins. no external loading ca- pacitors are needed. please note that the crystal must be placed very close to xtl1 and xtl2 pins of the cs8900a. this crystal oscillator can be eliminated if accurate clock signal (20.00 mhz 0.01% and 45-55 duty cycle) available in the system. isa bus interface the cs8900a has a direct isa bus interface. note that the isa bus interface is simple enough to allow the cs8900a to interface with variety of micro- processors directly or with the help of simple pro- grammable logic like a pal or a gal. this reference design uses the isa adapter card form factor. all the isa bus connections from the cs8900a are directly routed to the isa connector. the pin-out of the cs8900a is such that if the cs8900a is placed as shown in figures 6 and 7, there will be almost no cross-over of the isa sig- nals. external decode logic the cs8900a can be accessed in i/o mode or memory mode. for this reference design, in mem- ory mode the cs8900a is in the conventional or upper memory of the pc. that is, it resides in the lower 1 mega bytes of address space. to use the cs8900a in extended memory address space requires an external address decoder. this decoder decodes upper 4 bits (la[20:23]) of 24 bit isa address lines. in many embedded micropro- cessors such decodes are available though the mi- croprocessors itself. please refer to extended memory mode on page 31 for further information. eeprom a 64 word (64 x16 bit) eeprom (location u3) is used in the reference design to interface with the cs8900a. this eeprom holds the ieee as- signed ethernet mac (physical) address for the- board (see obtaining ieee addresses on page 55). the eeprom also holds other configu- ration information for the cs8900a. the last few bytes of the eeprom are used to store information about the hardware configuration and software re- quirements. in an embedded system, such as a pc, the system cmos ram or any other non-volatile memory can be used to store the ieee address and ethernet configuration information. in such a case an ee-
AN83 16 AN83rev2 figure 6. placement of components, top side cs8900 eval rev. b cdb8900b ?copyright 1994 crystal semiconductor corporation cs8900 eval board rev. b p/n cdb8900b
AN83 AN83rev2 17 figure 7. placement of components, solder side crystal semiconductor corporation cs8900 eval board rev. c p/n cdb8900b
AN83 18 AN83rev2 prom is not necessary for the cs8900a, and the cs8900a will respond to io addresses 0300h through 030fh after a reset. please refer to the cs8900a data sheet for informa- tion about programming the eeprom. please re- fer to jumperless design on page 45 of this document for information about eeprom in- ternal word assignments. leds many embedded systems do not require leds for the ethernet traffic. therefore this reference de- sign does not implement any leds. however, the cs8900a has direct drives for the three leds. please refer to the data sheet for the cs8900a for a description of the led functions available on the cs8900a. 10base-t interface the 10base-t interface for the cs8900a is straight forward. please refer to figure 8 (3.3v) and figure 10 (5v) for connections and compo- nents of this circuit. transmit and receive signal lines from the cs8900a are connected to an isola- tion transformer at location t1. this isolation transformer has a 1:1 ratio between the primary and the secondary windings on the receive side. it has a 1: ? 2 (1:1.414) ratio between the primary and the secondary windings for the transmit lines for 5v operation or a ratio of 1:2.5 for 3.3v operation. re- sistor r1 provides termination for the receive lines. resistors r2 and r3 are in series with the differen- tial pair of transmit lines for impedance matching. 10base-2 and aui interfaces as many embedded systems require only a 10base-t interface, this reference design imple- ments only the 10base-t interface. however, should a user require a 10base-2 or aui inter- face, the cs8900a provides a direct interface to the aui. please refer to low cost ethernet combo card reference design: crd8900 on page 21 of this document for details about the aui interface. logic schematics figures 8, 9 and 10 detail the logic schematics for the various circuits used in the reference design. 10bt_rd- 100 r2 8 r4 8 r5 .1uf .1uf c23 .1uf 2kv c28 .1uf 2kv c29 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1 2 3 4 5 6 7 8 16 (1-3) (16-14) 1:1 (6-8) (11-9) 1:2.5 10baset transformer 15 14 13 12 11 10 10 j21 9 16 15 14 13 12 11 10 9 9 do not populate 560pf c30 10bt_rd+ 10bt_td- 10bt_td+ do not populate figure 8. 10base-t schematic 3.3v
AN83 AN83rev2 19 sa00 sa01 sa02 sa03 sa04 sa05 sa06 sa07 sa08 sa09 sa10 sa11 sa12 sa13 sa14 sa15 sa16 sa17 sa18 sa19 isa0 isa1 isa2 isa3 isa4 isa5 isa6 isa7 isa8 isa9 isa10 isa11 isa12 isa13 isa14 isa15 isa16 isa17 isa18 isa19 37 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54 58 59 60 chipsel memw memr iow ior refresh sbhe aen 7 28 29 62 61 49 36 63 smemw smemr iow ior refresh sbhe aen 76 77 75 tstsel reset testsel sleep reset +5v xtal 20.0 mhz x1 1 2 97 98 93 xtl1 xtl2 res r4 4.99k, 1% elcs dvss3a dvss1a dvss4 dvdd4 dvss3 dvdd3 dvss2 dvdd2 dvss1 dvdd1 avss3 avdd3 avss2 avdd2 avss1 avdd1 avss4 avss0 eedatain eesk 2 57 10 70 69 55 56 23 22 8 9 94 95 86 85 89 90 96 1 6 4 c12 c14 c13 c9 c8 c11 c10 0.1 m f +5v ee_clk +5v 0.1 m f c7 1 2 3 5 8 4 7 6 vcc d0 nc2 nc1 1k_eeprom_s cs clk d1 vss u3 eecs eedataout 3 5 12 u1 cs8900 rxd+ txd- txd+ intrq0 intrq1 intrq2 intrq3 memcs16 i0cs16 i0chrdy dmarq0 dmarq1 dmarq2 csout 91 88 87 32 31 30 35 34 33 64 15 13 11 17 10bt_rd+ 10bt_td- 10bt_td+ irq10 irq11 irq12 irq5 memcs16 i0cs16 i0chrdy drq5 drq6 drq7 isa_d0 isa_d1 isa_d2 isa_d3 isa_d4 isa_d5 isa_d6 isa_d7 isa_d8 isa_d9 isa_d10 isa_d11 isa_d12 isa_d13 isa_d14 isa_d15 65 66 67 68 71 72 73 74 27 26 25 24 21 20 19 18 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 dmack0 dmack2 dmack3 16 14 12 dack5 dack6 dack7 80 79 82 81 84 83 78 100 99 rxd- 92 10bt_rd- di- di+ ci- ci+ do- do+ bstatus / hc1 led2 led0/hc0 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f figure 9. overall schematic
AN83 20 AN83rev2 component placement and signal routing please refer to layout considerations for the cs8900a on page 35 of this document for more details on the placement of components on the board. it is important to provide very clean and ad- equate +5 v and ground connections to the cs8900a. bill of material table 1 has a list components that are typically used to assemble this adapter card. for most of the components, there are several alternative manufac- turers. 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 (1-3) (16-14) 1:1 (6-8) (11-9) 1:1.414 10 baset transformer 100 r2 24.3 r4 24.3 r5 68 pf c30 .1 m f c23 do not populate .1 m f 2kv c29 .1 m f 2kv c28 j1 10 8 7 6 5 4 3 2 1 9 .1 m f do not populate 10bt_rd- 10bt_rd+ 10bt_td- 10bt_td+ figure 10. 10base-t schematic 5v c17 tant tant tant 22 m f22 m f22 m f c16 c15 + +5v gnd + + figure 11. decoupling capacitors schematic item reference # description quantity vendor part number 1 c2, c5, c7..c14 capacitor, 0.1 f, x7r, smt0805 10 2 c15, c16, c17 capacitor, 22 f, smt7343 3 3 r2, r3 resistor, 24.3, 1%, 1/8w, smt0805 2 4 r1 resistor, 100, 1%, 1/8w, smt0805 1 5 r4 resistor, 4.99k, 1%, smt0805 1 6* x1 crystal, 20.000 mhz 1 m-tron ats-49,20.000 mhz,18 pf 7 j1 connector, rj45, 8 pin 1 amp 555164-1 8 t1 transformer, 2, 1:1, 1:1.41 1 valor st7011 (soic) 9 u1 isa ethernet controller 1 crystal cs8900a 10* u3 1k eeprom 1 microchip 93c46 (8 pin soic) * depending on system resources, these parts may not be needed. table 1. cs8900a design bill of materials
AN83 AN83rev2 21 low cost ethernet combo card reference design: crd8900 this section describes the hardware design of a low- cost, two-layer, full-featured ethernet solution in- tended for use in pc isa-bus. the goal of this design is a high degree of application flexibility. therefore, a number of features (bootprom, aui, 10base-2) are supported. an example of this circuit is included in this technical reference manual. general description the cs8900a isa ethernet controller is used in this low cost, high performance isa ethernet adapter card. this card has aui, 10base-t and 10base-2 interfaces. the very high level of inte- gration of the cs8900a results in a very low com- ponent count. this makes it possible to design a half height, two layered 16 bit isa ethernet adapter card. since the analog filters are integrated on the cs8900a, the card may be compliant with fcc part 15 class (b) compliant. board design a recommended component placement is shown in figure 12, and a recommended board schematics are shown in figures 10 and 13 through 17. crystal oscillator the cs8900a, in the reference design, uses a 20.000 mhz crystal oscillator. please note that the crystal must be placed very close to xtl1 and xtl2 pins of the cs8900a. isa bus interface the isa bus connections from the cs8900a can be easily routed to the isa connector. if the pin-out of the cs8900a is placed as shown in figure 12, there will be almost no cross-over of the isa signals. it is also important to provide very clean and ade- quate +5 v and ground connections to the cs8900a. external decode logic the cs8900a can be accessed in both i/o and memory modes. the cs8900a internally decodes the sa[0:19] address lines for the lower 1 m of memory. the reference design uses an external de- code logic to allow the card to also decode decodes the upper 4 bits of the isa address (la[23:20]), thus allowing the cs8900a to reside anywhere in extended memory. this decode logic is implement- ed using a 16r4 pal at location u4. this logic is configured by the cs8900a. the pal then de- codes the upper 4 bits of the isa address. please re- fer to addressing the cs8900a: i/o mode, memory mode on page 27 of this document for further information. eeprom a 64 word (64 x16) eeprom (location u3) is used in the reference design to interface with the cs8900a. this eeprom holds the ieee as- signed ethernet mac (physical) address for the board. (see embedded designs on page 54) the eeprom also holds other configuration informa- tion for the cs8900a. the last few bytes of the eeprom are used to store information about the hardware configuration and software requirements. please refer to the cs8900a datasheet for informa- tion about programming the eeprom. please re- fer to jumperless design on page 45 of this document for information about eeprom in- ternal word assignment. socket for optional boot prom a socket is provided at location u6 for the optional boot prom. this boot prom is required in sys- tems that require remote boot capability, for exam- ple diskless work stations. the 74ls245 data buffer at u7 is provided for the boot prom (see figure 15). inside the cs8900a there are registers that hold the boot prom base address (pack- etpage base + 030h) and the boot prom address mask (packetpage base + 034h). a 20 bit address
AN83 22 AN83rev2 u6 cs8900 combo eval rev. b cdb8900b ?copyright 1994 crystal semiconductor corporation cs8900 combo eval board rev. b p/n cdb8900b c1 c2 u6 u7 c10 c4 c7 c8 u1 c3 u4 c17 c16 + + c6 c9 c11 r3 c12 c13 r4r5 x1 r2 c30 u3 c5 1 r6 c14 r7 r8 c15 r9 c18 u5 c1p + c20 r10 u2 c21 t1 u9 c27 j3 d1 r16 r17 r15 c24 r11 r12 r13 r14 t2 c26 f1 c29 c23 t3 c22 c28 r19 j1 j4 led1 t b r18 j2 figure 12. placement of components
AN83 AN83rev2 23 sa00 sa01 sa02 sa03 sa04 sa05 sa06 sa07 sa08 sa09 sa10 sa11 sa12 sa13 sa14 sa15 sa16 sa17 sa18 sa19 isa0 isa1 isa2 isa3 isa4 isa5 isa6 isa7 isa8 isa9 isa10 isa11 isa12 isa13 isa14 isa15 isa16 isa17 isa18 isa19 37 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54 58 59 60 chipsel memw memr iow ior refresh sbhe aen 7 28 29 62 61 49 36 63 chipsel memw memr iow ior refresh sbhe aen 76 77 75 tstsel reset testsel sleep reset +5v xtal 20.0 mhz x1 12 elcs 97 98 93 xtl1 xtl2 res r3 4.99k elcs dvss3a dvss1a dvss4 dvdd4 dvss3 dvdd3 dvss2 dvdd2 dvss1 dvdd1 avss3 avdd3 avss2 avdd2 avss1 avdd1 avss4 avss0 eedatain eesk 2 57 10 70 69 55 56 23 22 8 9 94 95 86 85 89 90 96 1 6 4 c16 c17 c8 c7 c11 c13 c12 0.1 m f +5v ee_clk ee_din ee_clk +5v 0.1 m f c5 1 2 3 5 8 4 7 6 vcc d0 nc2 nc1 1k_eeprom_s cs clk d1 vss u3 eecs eedataout 3 5 12 u1 cs8900 rxd- rxd+ txd- txd+ intrq0 intrq1 intrq2 intrq3 memcs16 i0cs16 i0chrdy dmarq0 dmarq1 dmarq2 csout 92 91 88 87 32 31 30 35 34 33 64 15 13 11 17 prom cs 10bt_rd- 10bt_rd+ 10bt_td- 10bt_td+ irq10 irq11 irq12 irq5 memcs16 i0cs16 i0chrdy drq5 drq6 drq7 prom_cs isa_d0 isa_d1 isa_d2 isa_d3 isa_d4 isa_d5 isa_d6 isa_d7 isa_d8 isa_d9 isa_d10 isa_d11 isa_d12 isa_d13 isa_d14 isa_d15 65 66 67 68 71 72 73 74 27 26 25 24 21 20 19 18 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 dmack0 dmack2 dmack3 16 14 12 da ck5 dack6 dack7 di- di+ 80 79 ci- ci+ 82 81 do- do+ 84 83 di- di+ ci- ci+ do- do+ bstatus / hc1 led2 78 100 led0/hc0 99 bstatus / hc1 r18 680 r19 680 3 1 4 2 led_t led_b 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f figure 13. cs8900a schematic (combo card application)
AN83 24 AN83rev2 figure 14. power supply decoupling schematic figure 15. boot prom schematic c19 tant tant tant 22 m f22 m f22 m f c10 c1 + +5v gnd + + sa00 sa01 sa02 sa03 sa04 sa05 sa06 sa07 sa08 sa09 sa10 sa11 sa12 sa13 sa14 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 27c256 ce oe vpp prom_cs 1 22 20 19 18 17 16 15 13 12 11 pd7 2 pd6 3 pd5 4 pd4 5 pd3 6 pd2 7 pd1 8 pd0 9 a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 18 17 16 15 13 12 11 14 oe dir 1 19 r1 4.7k +5v c4 0.1 m f u7 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 74ls245 u6 c2 0.1 m f
AN83 AN83rev2 25 figure 16. aui schematic figure 17. 10base-2 schematic figure 18. pal decode of la[20-23] +12v 0.1 m f bstatus/hci 1 2 4 5 7 8 16 15 13 12 10 9 aui_xfr_s t1 i11 i12 i21 i22 i31 i32 o11 o12 o21 o22 o31 o32 do+ ci- ci+ di- di+ do- 14 13 12 4 3 2 tx+ rx- rx+ cd- cd+ c18 0.1 m f 1 2 3 22 23 24 +12in1 +12in2 en en -12in1 -12in2 sout+ sout- 12 9 13 nc u5 dc-dc conversion c21 0.1 m f isolated_gnd -9_v 1082 do- 1082 do+ 1082 di- 1082 di+ 1082 ci- 1082 ci+ r10 1k tx- hbe rr+ rr- vee5 vee4 vee3 vee2 vee1 vee6 vee9 vee8 vee7 vee10 vee12 vee11 vee13 18 15 19 10 9 8 7 6 5 20 11 23 22 21 25 24 cds tx0 rx1 gnd1 gnd2 nc 1 28 26 16 17 27 cs83c92c_s u2 cds tx0 rx1 d1 1h916 c20 r15 10k r16 121 j3 bnc_50 1 2 c24 1kv .01 m f 1m 1/2w r17 do- do+ ci- ci+ di- di+ r6 39.2 r8 39.2 w r9 39.2 r7 39.2 c14 ci- ci+ di- di+ 0.1 m f c15 1 2 4 5 7 8 16 15 13 12 10 9 aui_xfr_s t2 1 2 3 4 5 6 7 8 ci_a do_a di_a con_aui15psubo j2 9 10 11 12 13 14 15 16 17 ci_b do_b di_b 0.1 m f c27 +12v f1 vp_+12v i11 i12 i21 i22 i31 i32 o11 o12 o21 o22 o31 o32 0.1 m f 1 11 2 3 4 5 6 7 8 9 clk g 10 11 12 13 14 15 16 17 i/00 i/01 i/02 i/03 12 13 18 19 14 15 16 17 00 01 02 03 chipsel_b (cs8900 pin7) pal16r4 elcs eedout bale la23 la22 la21 la20 reset ee_sk (cs8900 pin2) cs8900 pin5) (isa b28) (isa c02) (isa c03) (isa c04) (isa c05) (isa b02) (cs8900 pin 4)
AN83 26 AN83rev2 loaded at the boot prom base address register in- dicates the starting location in host memory where the boot prom is mapped. the boot prom ad- dress mask indicates the size of the boot prom. the lower 12 bits of the mask are ignored and should be 000h. this limits the 434 boot prom size to increments of 4k bytes. the cs8900a will not generate an address decode for the boot prom until the boot prom base address register and the mask register are loaded. for example, say a 16k boot prom is used and it is to be located starting at address 0d0000h. before this boot prom is accessed, load the following registers with the val- ues shown in table 2. the address mask that will be used by the cs8900a is 0fc000h. the cs8900a will com- pare sa[19:14] with the value 0d0h. whenever there is a match, it will assert the signal csout to generate an address decode for the boot prom. in the reference design, the same signal is also used to enable the data buffer, 74ls245, at location u7. leds a pair of leds are provided in the reference design to indicate link ok and line active status. the pair of leds are packaged one on the top of the other at location led1. the top led is driven by the lin- kled pin while the bottom led is driven by the lanled pin of the cs8900a. the top led lights up when the cs8900a has the link pulse. the bot- tom led lights up when the cs8900a transmits or receives a packet or senses a collision. the leds are directly driven by the cs8900a. two 680 ohm resistors limit the current flowing through the led circuitry. 10base-t interface the 10base-t interface for the cs8900a is straight forward. please refer to figure 8 or 10 for connections and components of this circuit. trans- mit and receive signal lines from the cs8900a are connected to an isolation transformer at location t3. for 5v operation this isolation transformer has a 1:1 ratio between the primary and the secondary windings on the receive side and 1: ? 2 (1:1.41) ratio between the primary and secondary windings for the transmit lines. for 3.3v operation the receive side is 1:1 and the transmit side is 1:2.5. resistor r2 provides termination for the receive lines. re- sistors r4 and r5 are in series with the differential pair of transmit lines for impedance matching. aui interface please refer to figure 16 for connection of aui sig- nals to the cs8900a. the aui lines from the 15- pin sub-d connector (location j2) are connected to the cs8900a through an isolation transformer at t2. this isolation transformer has three windings for three pairs of differential aui signals: transmit, receive and collision. all three windings have a turns ratio of 1:1 between the primary and second- ary windings. circuitry consisting of r6, r7 and c14 provides impedance termination for the colli- sion differential pair. circuitry consisting of r8, r9 and c15 provides impedance termination for the receive differential pair. the +12 volt power going out to the aui connector is safeguarded by the fuse at f1. the aui interface at j2 can be used to connect external media access units (mau). these maus allow the aui interfaced to be used to interface with 10base-5 or 10base-f. register word offset packetpage base + hex value description 30h 0000h boot prom base address - low word 32h 000dh boot prom base address - high word 34h c000h boot prom address mask - low word 36h 000fh boot prom address mask - high word table 2. bootprom descriptions stored in cs8900a packetpage
AN83 AN83rev2 27 10base-2 interface a 10base-2 transceiver ic, the 83c92c, is used to generate a 10base-2 interface for the reference design. please refer to figure 17 for details about the components and connection. a 12 volt to -9 volt dc to dc voltage converter (lo- cation u5) is used to generate an isolated -9 volt supply for the 83c92c. the dc-dc converter used in the reference design has an enable pin. this enable pin is connected to the hc1 pin of the cs8900a. usually the dc-dc converter is dis- abled when the 10base-2 interface is not used. this not only reduces power used by the adapter card but also eliminates any noise the 10base-2 circuitry can induce on the 10base-t or aui in- terface that may be in use. this reference design uses a low enable dc-dc converter. that is, the dc-dc converter is enabled when the enable pin is logic low. however, the board can be built with a high enable dc-dc converter. in such a case, software that controls the enable and disable oper- ations of the dc-dc converter should be modified. an optional method is to use an integrated module that includes all the needed 10base2 components. contact halo electronics for information on their tnt integrated 10base2 modules. logic schematics figures 10 and 13 through 17 detail logic schemat- ics for the various circuits used in the reference de- sign. component placement and routing of sig- nals figure 12 shows the component placement used for the reference design. figure 19 shows the routing of signals on the component side of the printed cir- cuit board (pcb) while figure 20 shows routing on the solder side. please refer to layout consider- ations for the cs8900a on page 35 of this docu- ment for an explanation and information about placement of components on the board. bill of material table 3 contains a list of components that are typi- cally used to assemble this adapter card. for most of the components, there are several alternative manufacturers. addressing the cs8900a: i/o mode, memory mode the cs8900a, integrated ethernet controller, has 20 address pins that directly connect to sa[19:0] of the isa bus. the cs8900a has an internal address comparator to compare the isa address with its base address registers. i/o mode in io mode, the lower 16 bits of the isa address are compared with the address stored in io base ad- dress register (packet page base + 020h). when an address match occurs and one of the io command (ior or iow ) lines is active, the cs8900a re- sponds to that io access. the lower 4 bits of ad- dress lines are ignored by the address comparator. this dictates that the cs8900a must always be at a 16 byte address boundary of the isa io address space. the pin chipsel is ignored for an io mode access. after reset the cs8900a responds to io address 0300h. however, this condition can be modified with use of an eeprom or by software. immedi- ately after a reset, the cs8900a reads the ee- prom interfaced to it. if the eeprom has valid data (valid start data and correct checksum), it will read information stored in the eeprom to initial- ize its own registers including the io base address register. please refer to the cs8900a datasheet for details about eeprom configuration and pro- gramming. a cs8900a will always respond to val- id io address (even if its memory mode is enabled).
AN83 28 AN83rev2 figure 19. crd8900 top-side routing
AN83 AN83rev2 29 figure 20. crd8900 bottom side routing
AN83 30 AN83rev2 item reference # description quantity vendor part number base configuration: i/o mode with 10base-t interface 1 c5, c7, c8, c11..13, c16, c17, c22, c23, c27 capacitor, 0.1 f, smt0805, x7r 11 2 c1, c10, c19 capacitor, 22 f, smt7343 3 3 r3 resistor, 4.99k, 1%, smt0805 1 4 r18, r19 resistor, 681, 5%, 1/8w, smt0805 2 5 x1 crystal, 20.000mhz,18 pf 1 m-tron ats-49 6 j4 board bracket 1 globe g436 7 u1 isa ethernet controller 1 crystal cs8900a 8 u3 1k eeprom 1 microchip 93c46 9 r4, r5 resistor, 24.3, 1%, 1/8w, smt0805 2 10 r2 resistor, 100, 1%, 1/8w, smt0805 1 11 c30 capacitor, 68 pf, smt0805 1 12 t3 transformer, 2, 1:1, 1:1.41 1 valor st7010 (soic) 13 j1 connector, rj45, 8 pin 1 amp 555164-1 memory mode option 1 c3 capacitor, 0.1 f, smt0805, x7r 1 2 u4 pal 1 amd pal16r4b boot prom options 1 c2, c4 capacitor, 0.1 f, smt0805, x7r 2 2 r1 resistor, 4.7k, 5%, 1/8w, smt0805 1 3 u6 32k x 8 eprom socket 1 4 u7 octal transceiver 1 ti 74ls245 (soic) aui option 1 c14, c15 capacitor, 0.1 f, smt0805, x7r 2 2 r6..r9 resistor, 39.2, 1%, 1/8w, smt0805 4 3 f1 fuse, 1a 1 4 t2 transformer, 3, 1:1, 100 h 1 valor st7033 (soic) 5 j2 connector, 15-pin sub-d 1 amp 745782-1 6 j2 aui slide latch 1 amp 745583-5 10base2 option 1 c18, c20, c21 capacitor, 0.1 f, smt0805, x7r 3 2 c24 capacitor, 0.01 f, 1kv 1 nic components ncd103m1kvz5u 3 r11..r14 resistor, 510, 1%, 1/8w, smt0805 4 4 r10 resistor, 1k, 1%, 1/8w, smt0805 1 5 r17 resistor, 1m, 10%, 1/2w, th 1 6 r15 resistor, 10k, 1%, 1/8w, smt0805 1 7 r16 resistor, 121, 1%, 1/8w, smt0805 1 8 d1 diode 1 1n916 9 t1 transformer, 3, 1:1, 100 h 1 valor st7033 (soic) 10 u2 ethernet coax transceiver 1 83c92c(plcc) 11 u5 dc-dc converter, 12v - 9v 1 valor pm7215 12 j3 connector, bnc, 50 ohm 1 amp 227161-7 led option 1 led1 bilevel leds 1 ledtronics 21pct110t4-g/y table 3. cs8900a combo card reference design bill of materials
AN83 AN83rev2 31 memory mode in the memory mode, there are two options where the cs8900a can be placed in the isa memory ad- dress map, lower memory (below 1 meg) or ex- tended memory (above 1 meg). the lower memory typically consists of the conventional memory (up to 640k) and upper memory (640k to 1 meg. boundary). to access anything in extended memory, the processor (386 and above) is used in the enhanced mode. the cs8900a will respond to io addresses pro- grammed in its io base address register (packet page base + 020h) even if memory mode is en- abled. to enable memory mode, first write a prop- er 20 bit value to memory base address register at packet page base + 02ch & 02eh. then set mem- orye (bit 0ah) in the bus ctl register (register 17) to one. these operations can be performed either by doing writes using io mode accesses or using an ee- prom as described in sections 3.4 and 3.5 of the cs8900a datasheet. the cs8900a will respond to an isa memory access, if the chipsel pin is active (low), and the sa[19:0] match the value stored in memory base address registers. the lower 12 bits of the address lines are always ig- nored. this dictates that the cs8900a must always be placed at a 4k boundary in the isa memory ad- dress space. lower memory mode to use a cs8900a in the lower 1 meg address space, smemrd and smemwr lines from the isa bus are connected to memr and memw pins of cs8900a respectively. the smemrd and smemwr signals become active only for the low- er 1 meg of the isa address space. the chipsel pin of the cs8900a should be connected to ground. extended memory mode the cs8900a can also be mapped in to the extend- ed memory of a personal computer (pc) system. this provides flexibility and more options when several components are installed in a pc with cs8900a based network cards. to address the cs8900a in extended memory mode, the processor is used in an enhanced mode. in an enhanced mode, 24 bits of isa address lines are used for address generation. since the cs8900a accepts 20 bits of address lines, an exter- nal address decoder circuit is required to decode the 4 upper address bits. the cs8900a has interface pins for external decoder circuit. this arrangement makes provisions so that the cs8900a can be placed anywhere in the extended memory address map as long as it is at a 4k address boundary. the memr and memw signals of the isa bus are active for any isa memory space ac- cess, therefore, for extended memory mode opera- tion, these signals are connected to the memr and memw pins of the cs8900a respectively. the external address decoder circuit consists of a single and simple programmable array logic like a 16r4 or gal16v8. please refer to the schematic shown in figure 21 as an example of such a decod- er circuit. the pal16r4 has 4 registers q[23:20]. these registers are programmed by the serial input via the inputs eesk (clock), elcs (enable pin) and eedataout (serial data out). this decoder compares the 4 upper address bits, namely la[23:20], with the internal programmable regis- ter, q[23:20]. before memory mode of the cs8900a is enabled, q[23:20] must be initialized to a proper value. in the design example, q[23:20] form a left shift register. the elcs pin of the cs8900a is used in- conjunction with eesk and eedataout pins to shift in the data for q[23:20] serially. to program a value, set the elsel bit (bit a in packet page base + 040h) to high. then the eeprom inter-
AN83 32 AN83rev2 face is used to generate the serial data stream on eedataout pin (serial data out) with the eesk (se- rial clock). whenever elsel bit is set, elcs pin becomes active (low) instead of eecs pin during the eeprom operations. since the eecs pin re- mains inactive, the eeprom that is interfaced to the cs8900a is not enabled. for the pal in the design example, one should use a program disable eeprom command. (opcode 00000b). for example, if the cs8900a is to be placed at pc memory space of 0a00000h, that means the q[23:20] should be 0ah. to program the 16r4, write 040ah at packet page base + 040h. the instruction will take about 10 micro-seconds to execute. the electrical connections required to use external logic are shown in figure 21. at reset, the cs8900a samples elcs pin and if it is not "low", it realizes presence of external address de- code logic. the same reset signal also makes add_valid inactive, and thus prevents a signal chipsel_b from becoming active until q[23:20] are initialized. when a host cpu writes to pack- etpage base address + 040h to program values for q[23:20], the cs8900a then shifts that data serial- ly in to the pal or gal. this makes add_valid signal active. from this point onwards la[23:20] are monitored whenever ale is active (high). when the decode logic finds a match, chipsel_b signal is asserted. this signal remains asserted until ale becomes active and the la[23:20] do not match with q[23:20]. the internal decoder of the cs8900a is active only when chipsel_b is active (low). 1 11 2 3 4 5 6 7 8 9 clk g 10 11 12 13 14 15 16 17 i/00 i/01 i/02 i/03 12 13 18 19 14 15 16 17 00 01 02 03 chipsel_b (cs8900 pin7) pal16r4 elcs eedout bale la23 la22 la21 la20 reset ee_sk (cs8900 pin2) cs8900 pin5) (isa b28) (isa c02) (isa c03) (isa c04) (isa c05) (isa b02) (cs8900 pin 4) figure 21. pal decode of la[20-23] cs8900 ethernet interface aui or 10 base-t terminating resistors isolation transformer or transformer with cmc connector figure 22. typical cs8900a ethernet connection
AN83 AN83rev2 33 figure 23 shows a simple palasmtm program for the 16r4 pal that is used in the design shown in figure 21. ;palasm design description ;---------------------------------- declaration segment ------------ title high address decoder pattern revision author deva bodas company crystal semiconductor date 04/01/1994 chip _decoder pal16r4 ;--------------------------------- pin declarations --------------- pin 1 sclk ; serial clock from the cs8900a pin 4 (eesk) pin 2 cs_el_b ; external logic enable from the cs8900a pin 2 (elcs*) pin 3 sdata ; serial data in from the cs8900a pin 5 (eedataout) pin 4 ale ; address latch enable from the isa bus pin 5 la23 ; address 23 pin 6 la22 ; address 22 pin 7 la21 ; address 21 pin 8 la20 ; address 20 pin 9 reset ; isa reset pin pin 11 oe ; output enable for the registered outputs pin 12 add_valid comb ; when high, q[23:20] are programmed pin 13 equalh comb ; upper 2 bits of address match pin 19 equall comb ; lower 2 bits of address match pin 18 chipsel_b comb ; chipsel to the cs8900a pin 7 pin 14 q20 ; reg pin 15 q21 ; reg pin 16 q22 ; reg pin 17 q23 ; reg ;----------------------------------- boolean equation segment ------ equations ; serial shift register ; when cs_el_b is inactive (1), no change ; when cs_el_b is active (0), shift in data
AN83 34 AN83rev2 q20 := (q20 * cs_el_b) + (/cs_el_b * sdata) q21 := (q21 * cs_el_b) + (/cs_el_b * q20) q22 := (q22 * cs_el_b) + (/cs_el_b * q21) q23 := (q23 * cs_el_b) + (/cs_el_b * q22) ; decode logic equall = (q20:*:la20) * (q21:*:la21) ; :*: -> exclusive nor operator equalh = (q22:*:la22) * (q23:*:la23) add_valid = /reset * cs_el_b * add_valid ; stay clear till any write + /reset * /cs_el_b ; set when address write + /reset * add_valid ; remain set until reset chipsel_b = reset ; get set at reset + /add_valid ; remain set till address is valid + (/ale * chipsel_b ; do not change when ale is low + (ale * /(equall * equalh)) ; clear during ale if address matches ; when ale is active; cs_b goes active if equal[1:2] are true ; when ale is inactive; previous state of cs_b is latched. figure 23. pal program
AN83 AN83rev2 35 layout considerations for the cs8900a the cs8900a is a mixed signal device having dig- ital and analog circuits for an ethernet communica- tion. while doing the pcb layout and signal connections, it is important to take the following precautions: - provide a low inductive path to reduce power and ground connection noise. - provide proper impedance matching especially to the ethernet analog signals. - provide low inductive path, wider and short traces, for all analog signals. it is important that a pcb designer follow sugges- tions made in this document for proper and reliable operation of the cs8900a. these guidelines will also benefit the design with good emi test results. general guidelines figure 24 shows component placement for an isa combo ethernet adapter card using a cs8900a. the placement of the cs8900a should be such that the routes of the analog signals and the digital sig- nals are not intermixing. no signal should route beneath the cs8900a on any plane. power supply connections the cs8900a has 3 analog and 4 digital power pin pairs (vcc and gnd). additional ground connec- tions are provided. each power pin pair should be connected to a 0.1 f bypass capacitor. connect the extra ground pins directly the ground plane. two layered printed circuit board (pcb) a two layered pcb has signal traces on the compo- nent and solder side of the pcb. fill unused areas with copper planes. typically, planes on the com- ponent side of the pcb are connected to ground and those on the solder side are connected to vcc or +5 volts. provide each pair of power pin with a 0.1 f bypass capacitor. place each bypass capacitor as close as possible to the corresponding power pin pair. con- nect the capacitor to the pads of the power pins by short, wide traces, the other end of these traces should be connected to vcc and gnd planes. fig- ure 19 and figure 20 illustrate ground and power (vcc) plane connections, respectively . multi-layered printed circuit board a multi-layered printed circuit board (pcb) typi- cally has separate ground and power (vcc) planes. multi-layered pcbs are required when the compo- nent and trace density is high. often discrete com- ponents like resistors and capacitors are placed on the solder side of a printed circuit board. for a multi-layer pcb with all components on one side of the board, follow the power connection guide lines as explained in two layered printed circuit board (pcb) on page 35. instead of con- necting the ground and vcc to the copper fills on the component and solder side of the board, con- nect them to the internal ground and vcc planes. figures 27 through 30 show the four layers of the four-layer card. for a multi-layered board the discrete components are to be placed on the solder side of the pcb, by- pass capacitors for the cs8900a can be placed on the solder side of the pcb. each bypass capacitor should be placed beneath the cs8900a and closest to its corresponding power pin pair. figures 31 and 32 illustrate the placement and routing of one bypass capacitor. routing of the digital signals most of the digital signals from the cs8900a go to the isa bus connector. route these signals directly to the connector. isolate the digital signals from analog signals. routing of the analog signals routing of the clock signals: place the 20.000 mhz crystal within one inch of xtl1 (pin #97) and xtl2 (pin #98) pins of the cs8900a.
AN83 36 AN83rev2 u6 cs8900 combo eval rev. b cdb8900b ?copyright 1994 crystal semiconductor corporation cs8900 combo eval board rev. b p/n cdb8900b c1 c2 u6 u7 c10 c4 c7 c8 u1 c3 u4 c17 c16 + + c6 c9 c11 r3 c12 c13 r4r5 x1 r2 c30 u3 c5 1 r6 c14 r7 r8 c15 r9 c18 u5 c1p + c20 r10 u2 c21 t1 u9 c27 j3 d1 r16 r17 r15 c24 r11 r12 r13 r14 t2 c26 f1 c29 c23 t3 c22 c28 r19 j1 j4 led1 t b r18 j2 figure 24. general placement on an isa adapter card
AN83 AN83rev2 37 figure 25. placement of components, top side cs8900 eval rev. b cdb8900b ?copyright 1994 crystal semiconductor corporation cs8900 eval board rev. b p/n cdb8900b
AN83 38 AN83rev2 figure 26. placement of components, solder side crystal semiconductor corporation cs8900 eval board rev. c p/n cdb8900b
AN83 AN83rev2 39 figure 2.4.6. component (top) side of four-layer board figure 27. component (top) side of four-layer board
AN83 40 AN83rev2 figure 2.4.7. +5v plane of four-layer board figure 28. +5v plane of four-layer board
AN83 AN83rev2 41 figure 2.4.8. ground plane of four-layer board figure 29. ground plane of four-layer board
AN83 42 AN83rev2 figure 2.4.9. solder side (bottom) of four-layer board figure 30. solder side (bottom) of four-layer board
AN83 AN83rev2 43 the 20.000 mhz crystal traces should be short, have no via, and run on the component side. biasing resistor at res pin of the cs8900a: a 4.99 k w resistor is connected between pins res (pin #93) and avss3 (pin #94) of the cs8900a. this resistor biases internal analog circuits of the cs8900a, and should be placed as close as possi- ble to res pin (pin #93) of the cs8900a. routing of the 10base-t signals: four signals are used for 10base-t communication, two dif- ferential transmit signals and two differential re- ceive signals. an isolation transformer is placed between the transmit and receive traces and a rj-45 (modular phone jack) connector. the isolation transformer should be placed as close as possible to the rj-45 connector. both transmit and receive signal traces should be routed so they are parallel and of equal length. the signal traces should be on the component side and should have direct and short paths. the widths of the receive signal traces should at least be 25 mil. while widths of the trans- figure 31. placement of decoupling capacitor (bottom side, under cs8900a) figure 32. routing of decoupling capacitor (top side, component side)
AN83 44 AN83rev2 mit signal traces should be at least 100 mil. this will provide a good impedance matching for the transmit and receive circuitry inside the cs8900a. a ground trace should be run parallel to the trans- mit traces. also, a ground plane should run under- neath the transmit and receive traces on the solder side of a two layered pcb. please refer to the fig- ures 33 and 34 for illustration of the above guide lines. routing of the aui signals: the cs8900a has three pairs of differential signals connecting it to an auxiliary unit interface (aui). an isolation trans- former separates the three signal pairs and the aui connector (a 15 pin sub-d connector). the isola- tion transformer should be placed as close as possi- ble to the aui connector. signal traces of each differential pair should be in parallel with equal length and impedance. thus minimizing differen- tial noise due to impedance mismatch. place the aui signal traces on the component side. recommended magnetics for the cs8900a the cs8900a is has two types of ethernet interfac- es 10base-t and aui. for both the interfaces, analog filters are on the chip. the figures 10 and 16 show typical connection required for these inter- faces. for an aui interface, an isolation transformer without a common mode choke (cmc) is used. for the 10base-t interface, choice between isola- tion transformer and isolation transformer with a common mode choke (cmc) depends on the com- mon mode noise that exists on the 10base-t lines in a particular system. a common mode choke re- duces common mode noise emitted by the 10base-t lines. a cmc may be required in cer- tain applications to meet emi requirements and to meet 10base-t common mode output voltage noise specification. the physical dimensions of the isolation transformer and the isolation transformer with a cmc are the same. both are typically avail- figure 33. 10base-t transit layout details
AN83 AN83rev2 45 able in a 16 pin dip or 16 pin soic package. see tables 4 and 5 for recommended part numbers. jumperless design using the cs8900a, both add-in adapters and motherboard solutions can be implemented without hardware jumpers or switches. the cs8900a and media access control (mac) device drivers obtain configuration information directly from nonvola- tile memory. for add-in isa adapters, a serial ee- prom will be connected directly to the cs8900a via the serial interface. motherboard solutions may use an on-board serial eeprom or other non- volatile memory such as a flash eprom-based bios. typically, a separate software utility is used to initially store and modify the configuration in- formation. serial eeprom two types of configuration information is stored in the eeprom: configuration information automat- ically loaded into the cs8900a after each reset and driver configuration information used by the mac driver. reset configuration block after each reset (except eeprom reset) the cs8900a checks to see if an eeprom is connect- ed. if an eeprom is present, the cs8900a auto- matically loads the first block of data stored in the eeprom into its internal registers. this block of data is referred to as the reset configuration block. it is used to initialize the cs8900a after each reset. software resets may occur frequently and perfor- mance will be enhanced if chip re-initialization takes as little time as possible. therefore, since ee- prom readout takes approximately 25 sec. per word, the length of the reset configuration block should be kept to a minimum. the mac drivers provided by cirrus will retain much of the adapters configuration across soft- figure 34. 10base-t receive layout details
AN83 46 AN83rev2 ware resets. therefore, the only information re- quired in the reset configuration block when used with cirrus-provided drivers will be the io base ad- dress (if different than the default 300h) and boot prom configuration when a boot prom is used. table 7 shows an example of a typical reset con- figuration block for an adapter with a boot prom. the first word of the block indicates the type of ee- prom in use and the length of the reset configu- ration block (the number of bytes loaded into the cs8900a after reset). the last word of the block contains an 8-bit checksum (in the high byte) of all the bytes in the block. refer to the cs8900a data vendor name description through-hole surface-mount halo electronics isolation transformer, 100 h td01-1006k tg01-1006n pulse engineering isolation transformer, 100 h pe-64503 pe-65728 valor electronics isolation transformer, 100 h lt6033 st7033 table 4. partial list of recommended aui transformers vendor name description through-hole surface-mount halo electronics transformer 1:1::1:1.41 td42-2006q tg42-1406n1 transformer with cmc td43-2006k tg43-1406n industrial temperature 1:1::1:1.41 tg42-2006n1 industrial temperature 1:1::1:1.41 with cmc tg43-2006n 3.3v commercial/industrial temperature 1:1::1:2.5 tg92-2006n1 3.3v commercial/industrial temperature with cmc tg41-2006n for pcmcia versions contact halo pulse engineering isolation transformer 1:1::1:1.41 pe-65994 pe-65745 transformer with cmc pe-65998 pe-65746 3.3v transformer 1:1::1:2.5 with cmc e2023 3.3v industrial temperature 1:1::1:2.5 with cmc ex2024 valor electronics isolation transformer 1:1::1:1.41 pt4069 st7011 transformer with cmc pt4068 st7010 table 5. partial list of recommended 10base-t transformers company and address telephone fax halo electronics, inc. redwood city, ca 94063 http://www.haloelectronics.com (415)-568-5800 (415)-568-6161 pulse engineering po box 12235 san diego, ca 92112 http://www.pulseeng.com (619)-674-8100 (619)-674-8262 valor electronics (merged with pulse) 9715 business park avenue, san diego, ca 92131 http://www.pulseeng.com (619)-537-2500 (619)-537-2525 table 6. transformer vendors
AN83 AN83rev2 47 sheet for additional information on the operation of the eeprom. driver configuration information the cs8900a supports random access to 16-bit words in the eeprom through software control. therefore, in addition to the configuration data stored in the reset configuration block automati- cally loaded by the cs8900a after each reset, addi- tional configuration information can be stored in the eeprom and accessed by the mac driver. typically, this additional configuration informa- tion includes the unique ieee physical address for the adapter. it may also contain device configura- tion information used by the mac driver such as hardware version, media capabilities, and bus con- figuration (irq, dma, and memory). format of driver configuration block table 8 defines the format of the block of configu- ration information (referred to as the driver con- figuration block) required for use with mac drivers provided by cirrus. cirrus recommends all fields be initialized to their default values before shipping the adapter. default values for each field are indicated in the following sections. all re- served fields should be set to zero. note: the driver configuration block must start at eeprom word address 1ch to ensure compatibil- ity with mac drivers supplied by cirrus. addr word description 00h a110h sequential eeprom, 16 bytes follow 01h 0020h 1 word into pp_020 (io base addr) 02h 0210h io base address = 210h 03h 3030h 4 words beginning at pp_030 04h 8000h boot prom base at c8000h 05h 000ch 06h c000h boot prom mask of fc000h (16k) 07h 000fh 08h 1600h checksum table 7. eeprom reset configuration block addr. description bit(s) function 1ch ia bits[39-32], bits[47-40] 15-0 ieee individual node address 1dh ia bits[ 23-16], bits[31-24] 15-0 ieee individual node address 1eh ia bits[ 7-0], bits[15-8] 15-0 ieee individual node address 1fh isa configuration flags memory mode flag 15 0 = memory mode disabled, 1 = memory mode enabled boot prom flag 14 0 = no boot prom, 1= boot prom installed streamtransfer 13 0 = disabled, 1 = enabled dma burst 12 0 = disabled, 1 = enabled rxdma only 11 0 = disabled, 1 = enabled auto rxdma 10 0 = disabled, 1 = enabled dma buffer size 9 0 = 16k, 1 = 64k iochrdy enable 8 0 = disabled, 1 = enabled use sa 7 0 = disabled, 1 = enabled dma channel 6-4 0 = drq5, 1 = drq6, 2 = drq7, 3 = dma disable irq 3-0 0 = irq10, 1 = irq11, 2 = irq12, 3 = irq5 20h packetpage mem base 15-4 12 msbs of 24-bit address (lower 12 bits assumed = 0) reserved 3-0 reserved for future use, set to 0 21h boot prom base 15-4 12 msbs of 24-bit address (lower 12 bits assumed = 0) reserved 3-0 reserved for future use, set to 0 22h boot prom mask 15-4 12 msbs of 24-bit addr mask (lower 12 bits assumed = 0) reserved 3-0 reserved for future use, set to 0 table 8. eeprom driver configuration block
AN83 48 AN83rev2 23h transmission control hdx/fdx 15 0 = half-duplex, 1 = full-duplex reserved 14-7 reserved for future use, set to 0 ignore missing media 6 0 = media required for driver to load, 1 = media not required reserved 5-0 reserved for future use, set to 0 24h adapter configuration ext. 10b-2 cable circuitry 15 0 = not present, 1 = present lorx squelch 14 0 = lorx squelch disabled, 1 = lorx squelch enabled polaritydis 13 0 = polarity correction enabled, 1 = pol. correction disabled 24h adapter configuration (continued) optimization flags 12-11 00 = server, 01 = dos client, 10 = multi-os client reserved 10-8 reserved for future use, set to 0 dc/dc converter polarity 7 0 = low enable, 1 = high enable media type in use 6-5 0 = auto detect, 1 = 10base-t, 2 = aui, 3 = 10base-2 la decode circuitry 4 0 = not present, 1 = present (reqd for decode above 1mb) hw standby 3 0 = hw standby not supported, 1 = hw standby supported 10base-2 circuitry 2 0 = not present, 1 = present aui circuitry 1 0 = not present, 1 = present 10base-t circuitry 0 0 = not present, 1 = present 25h eeprom revision 15-0 revision number of the eeprom format definition used 26h reserved 15-0 reserved for future use, set to 0 27h mfg date year 15-9 e.g. 1011111b = 1995, 0000001b = 2001 month 8-5 e.g. 1b = jan, 1100b = dec day 4-0 e.g. 1b = 1, 11111b = 31 28-2ah ieee individual addr 47-0 copy of words at 1c-1eh 2bh reserved 15-0 reserved for future use, set to 0 2ch reserved 15-0 reserved for future use, set to 0 2dh reserved 15-0 reserved for future use, set to 0 2eh reserved 15-0 reserved for future use, set to 0 2fh checksum 15-0 word-wide checksum of words 1ch to 2fh (zero sum) 30h eisa id (low word) 15-0 eisa id bits[7-0], eisa id bits[15-8] 31h eisa id (high word) 15-0 eisa id bits[23-16], eisa id bits[31-24] 32h serial no (low word) 15-0 32-bit oem assigned serial number, bits[15-8], bits[7-0] 33h serial no (high word) 15-0 32-bit oem assigned serial number, bits[31-24], bits[23-16] 34h serial id checksum marker byte 15-8 constant 0ah in high byte of checksum word lfsr checksum 7-0 8-bit lfsr checksum of words 30h to 33h addr. description bit(s) function table 8. eeprom driver configuration block
AN83 AN83rev2 49 ieee physical address the format of the 48-bit ieee physical address as expected by the mac driver is illustrated by the follow- ing example. (must be initialized by oem before shipping adapter.) example physical address: 000102030405h isa configuration flags the isa configuration flags specify how the cs8900a will utilize isa system resources. bit 15 memory mode flag - indicates the cs8900a will use shared memory for io operations. refer to the cs8900a data sheet for a description of the shared memory interface. default is disabled. bit 14 boot prom flag - indicates a boot prom is installed. refer to the cs8900a data sheet for discussion of boot prom. (must be initialized by oem before shipping adapter.) bit 13 streamtransfer mode - refer to the cs8900a data sheet for description of steamtransfer mode. default is disabled. bit 12 dma burst - refer to busctl register of the cs8900a data sheet for a discussion of dma burst control. default is enabled. bit 11 rxdma only - refer to the cs8900a data sheet for a description of rxdma only mode. default is disabled. bit 10 auto rxdma - refer to the cs8900a data sheet for a description of auto rxdma mode. default is disabled. bit 9 dma buffer size - refer to the cs8900a data sheet for a discussion of dma buffer size. default is 16k. bit 8 iochrdy enable - refer to the busctl register, of the cs8900a data sheet for a dis- cussion of iochrdy control. default is enabled. bit 7 usesa - refer to the busctl register, of the cs8900a data sheet for a discussion of us- esa control. default is enabled. bits 6-4 dma channel select - refer to the cs8900a data sheet for a discussion of dma channel selection for the cs8900a. default is disabled. bits 3-0 irq channel select - refer to the cs8900a data sheet for the typical isa bus, cs8900a pin to pin connection. cirrus pre-written drivers expect the pins to be connected as de- scribed in the datasheet when running in an x86 system. addr word description 1ch 0100h 2 msb of address (byte reversed) 1dh 0302h middle 2 bytes (byte reversed) 1eh 0504h 2 lsb of address (byte reversed)
AN83 50 AN83rev2 packetpage memory base bits 15-4 12 msb of memory base address - the twelve most significant bits of the 24-bit address locating the base of the cs8900as packetpage memory. the lower twelve bits are as- sumed to be 0. default is 0. bits 3-0 reserved (set to 0) boot prom memory base bits 15-4 12 msb of memory base address - the twelve most significant bits of the 24-bit address locating the base of the cs8900as packetpage memory. the lower twelve bits are as- sumed to be 0. default is 0. bits 3-0 reserved (set to 0) boot prom mask bits 15-4 12 msb of boot prom addr. mask - twelve-bit boot prom address mask. the lower twelve bits are assumed to be 0. refer to the cs8900a data sheet for a discussion of the boot prom mask. default is 0. bits 3-0 reserved (set to 0) transmission control bit 15 full duplex mode - specifies full-duplex or half-duplex mode for transmission. default is 0 (half-duplex operation). bits 14-7 reserved (set to 0) bit 6 ignore missing media (imm) - specifies device drivers behavior if a cable or aui is not connected during driver initialization. the drivers behavior can be summarized by the fol- lowing four cases. default is 0. case 1 (imm = 0, media autodetect selected, cable not connected) driver disables tx/rx and unloads if dynamic load/unload is supported by os. case 2 (imm = 0, media type specified [10b-t,aui,10b-2], cable not connected) driver disables tx/rx and unloads if dynamic load/unload is supported by os. case 3 (imm = 1, media autodetect selected, cable not connected) driver disables tx/rx and unloads if dynamic load/unload is supported by os. case 4 (imm = 1, media type specified [10b-t,aui,10b-2], cable not connected) driver remains resident, reports "media type xxxxx not detected", and functions normal- ly if/when the specified cable type is connected. bits 5-0 reserved (set to 0)
AN83 AN83rev2 51 adapter configuration word bits 15-13 reserved (set to 0) bits 12-11 optimization flags used to specify the platforms os configuration to the driver. each driver configures the cs8900a for optimum performance based on the platforms os and driver architecture (ndis 2x, odi, ndis 3x, etc.). default is dos (single threaded os). bits 10-8 reserved (set to 0) bit 7 dc to dc converter polarity refer to 10base-2 interface on page 27. (must be initialized by oem before shipping adapter.) bit 6-5 media type in use specifies the type of media the driver should use (10base-t, aui, 10base-2) or if driver should auto-detect media in use. default is auto-detect. bit 4 adapter provides la decode circuitry specifies the presence of la decode circuitry on the adapter. refer to extended memory mode on page 31. (must be initialized by oem before shipping adapter.) bit 3 adapter provides hw standby circuitry specifies the presence of hardware standby circuitry on the adapter. refer to the cs8900a data sheet . (must be initialized by oem before shipping adapter.) bit 2 adapter provides 10base-2 circuitry specifies the presence of 10base-2 circuitry on the adapter. (must be initialized by oem before shipping adapter.) bit 1 adapter provides aui circuitry specifies the presence of aui circuitry on the adapter. (must be initialized by oem be- fore shipping adapter.) bit 0 adapter provides 10base-t circuitry specifies the presence of 10base-t circuitry on the adapter. (must be initialized by oem before shipping adapter.) eeprom revision specifies the revision level of the format definition used by this eeprom. a value of 0 indicates the first revision level, a value of 1 indicates the second revision level, and so on.
AN83 52 AN83rev2 manufacturing date this word is the adapters manufacture date encoded in 16 bits, yr-mo-dy format. (must be initialized by oem before shipping adapter.) bits 15-9 two least-significant digits of year seven bits for a range of 00 to 99 decimal. a roll-over to 00 will be interpreted as the year 2000. bits 8-5 month four bits for a range of 01 to 12. bits 4-0 day five bits for a range of 01 to 31. ieee physical address (copy) this field is a copy of the three words at address 1ch to 1eh. (must be initialized by oem before shipping adapter.) 16-bit checksum the checksum stored at the end of the block is the 2s complement of the 16-bit sum of all the preceding words in the driver configuration block. (the drivers access the configuration block as 16-bit words.) any carry out of the 16th bit is ignored. since this checksum value is calculated as the 2s complement of the sum of all the preceding words in the block, a total of 0 should result when the checksum value is added to the sum of the previous words. (must be initialized by oem before shipping adapter.) eisa id the two eisa words make up the 32-bit eisa product identification code. low word these 16 bits make up the 3-letter identifier string of the oems eisa id in 5-bit com- pressed ascii. (a = 00001, b = 00010, c = 00011, etc.) bits 7-0 high order 8 bits of 16-bit value bits 15-8 low order 8 bits of 16-bit value high word these 16 bits make up the oems product id no. the upper order 11 bits are the product id number and the lower order 5 bits are the revision number. bits 7-0 high order 8 bits of 16-bit value bits 15-8 low order 8 bits of 16-bit value
AN83 AN83rev2 53 serial number the two serial number words make up the unique 32-bit oem serial number for the adapter. low word bits 7-0 bits[7-0] of 32-bit serial number bits 15-8 bits[15-8] of 32-bit serial number high word bits 7-0 bits[31-24] of 32-bit serial number bits 15-8 bits[23-16] of 32-bit serial number serial id checksum word 34h contains an 8-bit lfsr checksum calculated on the eisa id and oem serial number (words 30h to 33h). the 8-bit lfsr checksum is placed in the low byte of 34h. the high byte is padded with the constant 0ah.
AN83 54 AN83rev2 maintaining eeprom information the contents of the eeprom may either be pre- programmed in a stand-alone eeprom program- mer or programmed after installation through the cs8900as serial interface. see the cs8900a data sheet for programming an eeprom via the cs8900as serial interface. the oem is left to de- termine the best procedure for programming ee- proms via a stand-alone eeprom programmer. cirrus has two utilities suitable for maintaining the configuration information stored in the eeprom. iagen.exe generates a file with individual ad- dresses and serial numbers. eeprom.exe is de- signed to be used by oems to initialize the eeproms contents before shipping to the end-us- er. it takes the file generated by iagen.exe as in- put. both utilities are available as executables and source code on request. cirrus also provides setup.exe, a dos-based setup and installation utility run by the end-user at the time the adapter is installed. the dos-based setup and installation utility allows the end-user to configure the adapter for a specific system. embedded designs embedded designs may be implemented using an on-board serial eeprom connected to the cs8900a in the same manner as is used in adapter board designs. however, to save board space and reduce costs, motherboard implementations can store the driver configuration block in the sys- tems bios nonvolatile memory. bios-based design considerations for cirrus supplied mac drivers to interface with a driver configuration block (dcb) stored in bios, the dcbs data structure must meet the fol- lowing requirements: 3) the base of the data structure must be marked by a header consisting of the 8-byte ascii text string $cs8900a$. 4) the header must be located on a 512-byte boundary in the bios space between c0000h and ffc00h. 5) the data structure must employ the same for- mat as defined for eeprom in table 8. an additional design consideration when storing the driver configuration block in bios space con- cerns the inability to override the cs8900as de- fault configuration after reset. if an eeprom is not connected to the cs8900a, it will always come out of reset using its default configuration. there- fore, when using bios space to store configuration information, io addresses of 300h - 310h must be dedicated to the cs8900a. the cs8900as configuration can be changed from its default values through software control af- ter reset. however, it will always revert to its de- fault configuration after each reset (including software resets). refer to table 3.3 of the cs8900a data sheet for default configuration definitions. driver interface with bios-based configu- ration during initialization, cirrus-provided drivers test for the presence of an eeprom. if an eeprom is not detected, the drivers scan the bios for the header indicating the start of a driver configura- tion block. before using the data in the driver configuration block, the drivers verify the data in the block is valid using a checksum. the checksum stored at the end of the block is the 2s complement of the 16-bit sum of all the words in the driver configuration block, excluding the 8 bytes of header. (the drivers access the configura- tion block in bios space as 16-bit words.) any carry out of the 16th bit is ignored. since this checksum value is calculated as the 2s comple- ment of the sum of all the preceding words in the block, a total of 0 should result when the checksum value is added to the sum of the previous words. table 9 shows the correct format for a data struc-
AN83 AN83rev2 55 ture storing the driver configuration block in bios space. obtaining ieee addresses each node of a local area network has a unique address for the media access control (mac). this makes it possible for that particular node to have unique identity for data communication. this ad- dress, known as the ieee physical address, con- sists of 48 bits of data. this address is assigned to a lan physical interface node by the manufacturer of the network interface card. to ensure uniqueness of the address, 24 bits of out of the 48 bits of the physical address are assigned to the manufacturer by the ieee standards commit- tee. this 24 bit address is known as organization- ally unique identifier (oui). the remaining 24 bits of the address are assigned by the manufactur- er. for further information and an application for an oui, please contact the ieee at the following address: ieee registration authority, ieee standards department, 445 hoes lane, po box 1331 piscataway, nj 08855-1331, usa telephone: (908) 562-3813 fax: (908) 562-1571 adapter boards shipped as part of cirrus cs8900a evaluation kit are programmed with an ieee physical address obtained from an allotment assigned to cirrus logic by the ieee. byte offset description function 00h header 8 bytes = $cs89xx$ 08h individual address ieee individual address. same format as word 1ch in table 8 0ah individual address ieee individual address. same format as word 1dh in table 8 0ch individual address ieee individual address. same format as word 1eh in table 8 0eh isa configuration flags same format as word 1fh in table 8 10h packet page base 12 msbs of 24-bit address (lower 12 bits assumed = 0) 12h boot prom base 12 msbs of 24-bit address (lower 12 bits assumed = 0) 14h boot prom mask 12 msbs of 24-bit addr mask (lower 12 bits assumed = 0) 16h transmission control same format as word 23h in table 8 18h adapter configuration same format as word 24h in table 8 1ah eeprom revision same format as word 25h in table 8 1ch reserved reserved for future use, set to 0 1eh mfg date same format as word 27h in table 8 20h-25h ieee individual addr copy of 6 bytes at offset 08h 26h reserved reserved for future use, set to 0 28h reserved reserved for future use, set to 0 2ah reserved reserved for future use, set to 0 2ch reserved reserved for future use, set to 0 2eh checksum word-wide checksum of words 08h to 2fh (zero sum) 30h eisa id (high word) same format as word 30h in table 8 32h eisa id (low word) same format as word 31h in table 8 34h serial number same format as word 32h in table 8 36h serial number same format as word 33h in table 8 38h ldsr checksum same format as word 34h in table 8 table 9. format of driver configuration block in bios space
AN83 56 AN83rev2 device drivers and setup/installation software this chapter discusses the software provided by cirrus for use with the cs8900a. that software in- cludes a broad family of device drivers, driver-re- lated data files, and utilities. a single-user, evaluation copy of that software is included with this kit. the following drivers are included in the kit: - novell odi 4.x dos (for use with netware clients) - novell odi 4.x os/2 driver (for use with netware os/2 clients) - novell odi 4.x server driver - microsoft ndis 3.x driver (for use with windows 95, 98, windows nt, and windows for workgroups) - microsoft ndis 2.x dos driver (for use with many noss including microsoft lan manager, ibm lan server, banyan vines, lantastic, dec pathworks) - microsoft ndis 2.x driver for os/2 - boot prom program (for odi and ndis) allowing a diskless pc to load a simple lan driver from prom and then use the simple driver to boot dos from a server over the network. also known as ripl (remote initial program load). - packet driver v1.09 (for use with tcp/ip protocol stacks, including pc/tcp, sun pc- nfs, wollongong) - sco unix driver and installation script additionally cirrus provides two utility programs: - dos setup and installation utility - eeprom programming utility, for use in oem manufacturing environments. additional drivers and links to other supported op- erating systems may be found on the cirrus web- site, http://www.cirrus.com. cirruss software licensing procedures the cs8900a developers kit contains a single- user copy of object code which is available only for internal testing and evaluation purposes. this ob- ject code may not be distributed without first sign- ing a license for distribution of executable software, which may be ob- tained by contacting your sales representative. the license for distribution of execut- able software gives you unlimited, royalty- free rights to distribute cirrus-provided object code. dos setup and installation utility setup.exe allows you to install a driver (in a non unix machine), and to configure a cs8900a- based adapter card. the utility will allow the user to select configura- tion settings, for example, interrupt number, dma channel, io base address and memory base ad- dress. the selected values are stored in the cs8900as eeprom and will thereafter be loaded from the eeprom, whenever the cs8900a ic is reset. the utility is menu driven. the menu items can be selected using either the mouse, or the arrow keys. the arrow keys are enabled by first typing the alt key. in an embedded or motherboard application (non- adapter-card application), there may not be an ee- prom attached to the cs8900a. in this case, the system bios may store the cs8900a configura- tion information in system memory such as system cmos. this utility is not applicable to such em- bedded or motherboard applications. installation procedure 1) install the cs8900a-based adapter card into the pc. the adapter must be installed to use the setup and installation utility. 2) place the dos setup and installation utility diskette into drive a: (or b:). 3) from a dos prompt, type: a:\setup (or b:\ setup)
AN83 AN83rev2 57 4) the current configuration of the adapter will be displayed. click on ok or press the enter key to proceed. 5) press the alt key then use the adapter/manu- al configuration options to manually override any of the current configurations setting shown. 6) use diagnostics/self test to test the function- ality of the card. 7) use the diagnostic/network test screen to test the ability of the card to communicate across the ethernet with another cs8900a-based card which is also running the dos setup and in- stallation utility. contacting customer support at cirrus cirrus logic is committed to providing the indus- trys most easily implemented ethernet solution. we invite you to contact us for assistance at any time during the design process. our application engineering department offers free schematic and layout review services and provides software sup- port for cirruss network drivers. let cirruss ap- plication engineers help you confirm the optimum design for your specific application. to contact cirrus application engineering, call (800) 888-5016 (from the us and canada) or 512- 442-7555 (from outside the us and canada), and ask for cs8900a application support, or send an email to: ethernet@crystal.cirrus.com. cirrus web site cirrus also offers free updates to the of the network driver software using the cirrus website: http://ww.cirrus.com.

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